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rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. ad8011 300 mhz current feedback amplifier features easy to use low power 1 ma power supply current (5 mw on 5 v s ) high speed and fast settling on 5 v 300 mhz, ? db bandwidth (g = +1) 180 mhz, ? db bandwidth (g = +2) 2000 v/ s slew rate 29 ns settling time to 0.1% good video specifications (r l = 1 k , g = +2) gain flatness 0.1 db to 25 mhz 0.02% differential gain error 0.06 differential phase error low distortion ?0 dbc worst harmonic @ 5 mhz ?2 dbc worst harmonic @ 20 mhz single supply operation fully specified for 5 v supply applications power sensitive, high speed systems video switchers distribution amplifiers a-to-d driver professional cameras ccd imaging systems ultrasound equipment (multichannel) frequency (mhz) 1 normalized gain (db) 10 4 3 2 1 0 ? ? ? ? 5 ? g = +2 r f = 1k v s = +5v or 5v v out = 200mv p-p 100 500 figure 1. frequency response; g = +2, v s = +5 v, or 5 v functional block diagram 8-lead pdip and soic 1 2 3 4 8 7 6 5 nc v+ nc ?n v nc +in nc = no connect out ad8011 product description the ad8011 is a very low power, high speed amplifier designed to operate on +5 v or 5 v supplies. with wide bandwidth, l ow distortion, and low power, this device is ideal as a general- purpose am plifier. it also can be used to replace high speed amplifiers consuming more power. the ad8011 is a current feed- back am plifier and features gain flatness of 0.1 db to 25 mhz while offering differential gain and phase error of 0.02% and 0.06 on a single 5 v supply. this makes the ad8011 ideal for profes- sional video electronics such as cameras, video switchers, or any high speed portable equipment. additionally, the ad8011 s low distortion and fast settling make it ideal for buffering high speed 8-, 10-, and 12-bit a-to-d converters. the ad8011 offers very low power of 1 ma maximum and can run on single 5 v to 12 v supplies. all this is offered in a small 8-lead pdip or 8-lead soic package. these features fit well with portable and battery-powered applications where size and power are critical. the ad8011 is available in the industrial temperature range of C 40 c to +85 c. distortion (dbc) ?0 ?00 ?0 ?0 frequency (mhz) 10 20 third r l = 150 second r l = 150 third r l =1k second r l = 1k g = +2 figure 2. distortion vs. frequency; v s = 5 v
rev. c ? ad8011?pecifications dual supply ad8011a parameter conditions min typ max unit dynamic performance C 3 db small signal bandwidth, v o < 1 v p-p g = +1 340 400 mhz C 3 db small signal bandwidth, v o < 1 v p-p g = +2 180 210 mhz C 3 db large signal bandwidth, v o = 5 v p-p g = +10, r f = 500 ? 57 mhz bandwidth for 0.1 db flatness g = +2 20 25 mhz slew rate g = +2, v o = 4 v step 3500 v/ s g = C 1, v o = 4 v step 1100 v/ s settling time to 0.1% g = +2, v o = 2 v step 25 ns rise and fall time g = +2, v o = 2 v step 0.4 ns g = C 1, v o = 2 v step 3.7 ns noise/harmonic performance second harmonic f c = 5 mhz, v o = 2 v p-p, g = +2 r l = 1 k ? C 75 db r l = 150 ? C 67 db third harmonic r l = 1 k ? C 70 db r l = 150 ? C 54 db input voltage noise f = 10 khz 2 nv/ hz input current noise f = 10 khz, +in 5 pa/ hz C in 5 pa/ hz differential gain error ntsc, g = +2, r l = 1 k ? 0.02 % r l = 150 ? 0.02 % differential phase error ntsc, g = +2, r l = 1 k ? 0.06 degrees r l = 150 ? 0.3 degrees dc performance input offset voltage 25 mv t min C t max 26 mv offset drift 10 v/ c C input bias current 515 a t min C t max 20 a +input bias current 515 a t min C t max 20 a open-loop transresistance 800 1300 k ? t min C t max 550 k ? input characteristics input resistance +input 450 k ? input capacitance +input 2.3 pf input common-mode voltage range 3.8 4.1 v common-mode rejection ratio offset voltage v cm = 2.5 v C 52 C 57 db output characteristics output voltage swing 3.9 4.1 v output resistance 0.1 0.3 ? output current t min C t max 15 30 ma short-circuit current 60 ma power supply operating range 1.5 6.0 v quiescent current t min C t max 1.0 1.3 ma power supply rejection ratio v s = 5 v 1 v 55 58 db specifications subject to change without notice. (@ t a = 25 c, v s = 5 v, g = +2, r f = 1 k , r l = 1 k , unless otherwise noted.)
rev. c ad8011 ? single supply ad8011a parameter conditions min typ max unit dynamic performance C 3 db small signal bandwidth, v o < 0.5 v p-p g = +1 270 328 mhz C 3 db small signal bandwidth, v o < 0.5 v p-p g = +2 150 180 mhz C 3 db large signal bandwidth, v o = 2.5 v p-p g = +10, r f = 500 ? 57 mhz bandwidth for 0.1 db flatness g = +2 15 20 mhz slew rate g = +2, v o = 2 v step 2000 v/ s g = C 1, v o = 2 v step 500 v/ s settling time to 0.1% g = +2, v o = 2 v step 29 ns rise and fall time g = +2, v o = 2 v step 0.6 ns g = C 1, v o = 2 v step 4 ns noise/harmonic performance second harmonic f c = 5 mhz, v o = 2 v p-p, g = +2 r l = 1 k ? C 84 db r l = 150 ? C 67 db third harmonic r l = 1 k ? C 76 db r l = 150 ? C 54 db input voltage noise f = 10 khz 2 nv/ hz input current noise f = 10 khz, +in 5 pa/ hz C in 5 pa/ hz differential gain error ntsc, g = +2, r l = 1 k ? 0.02 % r l = 150 ? 0.6 % differential phase error ntsc, g = +2, r l = 1 k ? 0.06 degrees r l = 150 ? 0.8 degrees dc performance input offset voltage 25mv t min C t max 26m v offset drift 10 v/ c C input bias current 51 5 a t min C t max 20 a +input bias current 515 a t min C t max 20 a open-loop transresistance 800 1300 k ? t min C t max 550 k ? input characteristics input resistance +input 450 k ? input capacitance +input 2.3 pf input common-mode voltage range 1.5 to 3.5 1.2 to 3.8 v common-mode rejection ratio offset voltage v cm = 1.5 v to 3.5 v C 52 C 57 db output characteristics output voltage swing 1.2 to 3.8 0.9 to 4.1 +v output resistance 0.1 0.3 ? output current t min C t max 15 30 ma short-circuit current 50 ma power supply operating range +3 +12 v quiescent current t min C t max 0.8 1.15 ma power supply rejection ratio ? v s = 1 v 55 58 db specifications subject to change without notice. (@ t a = 25 c, v s = 5 v, g = +2, r f = 1 k , v cm = 2.5 v, r l = 1 k , unless otherwise noted.)
rev. c ? ad8011 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8011 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 v internal power dissipation 2 plastic dip package (n) . . . . . . . observe derating curves small outline package (r) . . . . . . observe derating curves input voltage (common mode) . . . . . . . . . . . . . . . . . . . . v s differential input voltage . . . . . . . . . . . . . . . . . . . . . . 2.5 v output short-circuit duration . . . . . . . . . . . . . . . . . .o bserve power derating curves storage temperature range (n, r) . . . . . . . C 65 c to +125 c operating temperature range (a grade) . . . C 40 c to +85 c lead temperature range (soldering 10 sec) . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for device in free air: 8-lead pdip package: ja = 90 c/w 8-lead soic package: ja = 155 c/w 2.0 1.5 0.5 ?0 ?0 ?0 ?0 ?0 0 10 20 30 40 50 60 70 80 90 ambient temperature (c) 1.0 0 maximum power dissipation (w) t j = 150c 8-lead plastic dip package 8-lead soic package figure 3. maximum power dissipation vs. temperature maximum power dissipation the maximum power that can be safely dissipated by the ad 8011 is limited by the associated rise in junction temperature. the maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150 c. exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junction temperature of 175 c for an extended period can result in device failure. while the ad8011 is internally short-circuit protected, this may not be sufficient to guarantee that the maximum junction tem- perature is not exceeded under all conditions. to ensure proper operation, it is necessary to observe the maximum power derating curves (shown in figure 3). 0.01f 0.01f 10f 10f r l 1k 1k 1k 50 v in v out +v s ? s figure 4. test circuit; gain = +2 0.01f 0.01f 10f 10f r l 1k 1k 1k v in v out +v s ? s 52.3 figure 5. test circuit; gain = ? ordering guide temperature package package model range description option ad8011an C 40 c to +85 c8 -lead pdip n-8 ad8011ar C 40 c to +85 c 8-lead soic r-8 ad8011ar-reel C 40 c to +85 c 13" tape and reel r-8 ad8011ar-reel7 C 40 c to +85 c 7" tape and reel r-8
rev. c t ypical performance characteristics?d8011 ? 20mv 5ns * tpc 1. 100 mv step response; g = +2, v s = 2.5 v or 5 v 800mv 10ns 4v step 2v step *tpc 2. step response; g = +2, v s = 2.5 v (2 v step) and 5 v (4 v step) 6.5 6.4 6.3 6.2 6.1 5.9 5.8 5.7 1 10 100 500 frequency ( mhz ) 6.0 5.6 5.5 gain (db) v s = +5v v s = 5v g = +2 v in = 100mv p-p r l = 1k r f = 1k tpc 3. gain flatness; g = +2 20mv 5ns *tpc 4. 100 mv step response; g = ?, v s = 2.5 v or 5 v 800mv 10ns 4v step 2v step *tpc 5. step response; g = ?, v s = 2.5 v (2 v step) and 5 v (4 v step) 9 8 7 6 5 3 2 10 100 1000 10000 load resistance ( ) 4 1 0 swing (v p-p) +5v 5v tpc 6. output voltage swing vs. load * note: v s = 5 v operation is identical to v s = +5 v single-supply operation.
rev. c ? ad8011 frequency (mhz) distortion (dbc) ?0 ?00 1 10 20 ?0 ?0 third r l =1k third r l = 150 second r l = 150 second r l = 1k g = +2 tpc 7. distortion vs. frequency; v s = 5 v 1k diff phase (degrees) 100 0 ire r l = 1k r l = 150 0.04 ?.04 0.00 ?.02 0.02 0.01 ?.01 ?.03 0.03 v s = 5v g = +2 0.4 ?.4 0.00 ?.2 0.2 0.1 ?.1 ?.3 0.3 150 diff phase (degrees) diff gain (%) r l = 150 100 0 ire r l = 1k 0.04 ?.04 0.00 ?.02 0.02 0.01 ?.01 ?.03 0.03 v s = 5v g = +2 tpc 8. diff phase and diff gain; v s = 5 v 6 3 0 ? ? ?2 ?5 ?8 1 10 40 100 500 frequency ( mhz ) ? 9 output voltage (dbv) ?1 1v rms tpc 9. large signal frequency response; v s = 5 v, g = +2 frequency ( mhz ) distortion (dbc) ?0 ?00 1 10 20 ?0 ?0 third r l =1k third r l = 150 second r l = 150 g = +2 second r l =1k tpc 10. distortion vs. frequency; v s = +5 v 0.08 1k diff gain (%) ?.08 0.00 ?.04 0.04 100 0ire 1k diff phase (degrees) 150 diff phase (degrees) 100 0 ire 0.02 ?.02 ?.06 0.06 0.8 ?.8 0.0 ?.4 0.4 0.2 ?.2 ?.6 0.6 0.08 ?.08 0.00 ?.04 0.04 0.02 ?.02 ?.06 0.06 r l =150 r l =1k r l =1k r l =150 v s = +5v g = +2 v s = +5v g = +2 150 diff gain (%) 0.8 ?.8 0.0 ?.4 0.4 0.2 ?.2 ?.6 0.6 tpc 11. diff phase and diff gain; v s = +5 v 0 ? ? ? ?2 ?8 ?1 ?4 1 10 40 100 500 frequency (mhz) ?5 3 output voltage (dbv) ?7 1v rms tpc 12. large signal frequency response; v s = +5 v, g = +2
rev. c ad8011 ? 4 3 2 1 0 ? ? ? 1 10 100 500 frequency ( mhz ) ? 5 normalized gain (db) ? g = +10 r f = 500 g = +2 r f = 1k g = +1 r f = 1k v s = +5v or 5v v out = 200mv p-p tpc 13. frequency response; g = +1, +2, +10; v s = +5 v or 5 v 1 0 ? ? ? 1 10 100 500 frequency ( mhz ) ? 2 normalized gain (db) ? ? ? ? g = ?0 r f = 500 r l = 1k v s = +5v or 5v v out = 200mv p-p g = ? r f = 1k r l = 1k tpc 14. frequency response; g = ?, ?0; v s = +5 v or 5 v ?0 ?5 ?0 ?5 ?0 ?0 ?5 ?0 0.1 1 10 100 frequency (mhz) ?5 ?5 ?0 cmrr (db) v s = +5v or 5v g = +2 tpc 15. cmrr vs. frequency; v s = +5 v or 5 v t = 0 output voltage (0.1%/div) 0.1% 5ns g = +2 r f = 1k 2v step tpc 16. short-term settling time; v s = +5 v or 5 v t = 0 output voltage (0.1%/div) 0.1% 100ns g = +2 r f = 1k 2v step tpc 17. long-term settling time; v s = +5 v or 5 v 10 0 ?0 ?0 ?0 ?0 ?0 ?0 100k 1m 10m 100m 500m frequency (hz) ?0 ?0 ?0 psrr (db) v s = +5v or 5v g = +2 r f = 1k +psrr ?srr tpc 18. psrr vs. frequency; v s = +5 v or 5 v
rev. c ? ad8011 100 10 0.1 10k 0.1m 1m 10m 100m 500m frequency ( hz ) 1 0.01 output resistance ( ) v s = +5v or 5v g = +2 r f = 1k tpc 19. output resistance vs. frequency; v s = +5 v or 5 v 1k 10k 100k 1m 10m 100m 1g 140 120 100 80 60 20 0 frequency (hz) 40 gain (db ) 0 phase (degrees) ?0 ?0 ?20 ?60 ?00 ?40 ?80 phase gain tpc 20. transimpedance gain and phase vs. frequency 12.5 10.0 5.0 2.5 500 1k 10k 100k frequency ( hz ) 7.5 0 50 40 20 10 30 0 input voltage noise (nv/ hz) input current noise (pa/ hz) tpc 21. noise vs. frequency; v s = +5 v or 5 v 9 8 7 6 5 4 3 2 3 4 5 6 7 8 9 10 11 1 0 f = 5mhz g = +2 r f = 1k r l = 150 r l = 1k total supply voltage (v) peak-to-peak output at 5mhz [ 0.5% thd] (v) tpc 22. output swing vs. supply
rev. c ad8011 ? theory of operation the ad8011 is a revolutionary generic high speed cf amplifier that attains new levels of bw, power, distortion, and signal swing capability. if these key parameters were combined as a figure of ac merit performance or [(frequency v sig )/(distortion power)], no ic amplifier today would come close to the merit value of the ad8011 for frequencies above a few mhz. its wide dynamic p erformance (including noise) is the result of both a new com- ple mentary high speed bipolar process and a new and unique architectural design. the ad8011 uses basically a two gain stage complementary design approach versus the traditional single stage complementary mirror structure sometimes referred to as the nelson amplifier. though twin stages have been tried before, they typically consumed high power since they were of a folded cascade design much like the ad9617. this design allows for the standing or quiescent current to add to the high signal or slew current induced stages much like the nelson or single-stage design. thus, in the time domain, the large signal output rise/fall time and slew rate is controlled typically by the small signal bw of the amplifier and the input signal step amplitude respectively, not the dc quiescent current of the gain stages (with the exception of input level shift diodes q1/q2). using two stages versus one also allows for a higher overall gain bandwidth product (gbwp) for the same power, thus lower signal distortion and the ability to drive heavier external loads. in addition, the second gain stage also isolates (divides down) a3 s input reflected load drive and the nonlinearities created resulting in relatively lower distortion and higher open-loop gain. overall, when high external load drive and low ac distortion is a requirement, a twin gain stage integrating amplifier like the ad8011 will provide superior results for lower power over the traditional single-stage complementary devices. in addition, being a cf amplifier, closed-loop bw variations versus external gain variations (varying rn) will be much lower compared to a vf op amp, where the bw varies inversely with gain. another key attribute of this amplifier is its ability to run on a single 5 v supply due in part to its wide common-mode input and output voltage range capability. for 5 v supply operation, the device obviously consumes half the quiescent power (versus 10 v supply) with little degradation in its ac and dc performance characteristics. see specifications. dc gain characteristics gain stages a1/a1b and a2/a2b combined provide negative feedforward transresistance gain (see figure 6). stage a3 is a unity gain buffer that provides external load isolation to a2. each stage uses a symmetrical complementary design. (a3 is also complemen- tary though not explicitly shown.) this is done to reduce second order signal distortion and overall quiescent power as discussed previously. in the quasi dc to low frequency region, the closed- loop gain relationship can be approximated as g = 1 + r f / r n noninverting operation g = C r f / r n inverting operation these basic relationships are common to all traditional opera- tional amplifiers. due to the inverting input error current (i e ) required to servo the output and the inverting i e r i drop v p q1 q2 ipp ipn ipn v n z i iq1 q3 q4 ie ir ?ifc ir + ifc c p 1 c p 1 z2 a2 c l r l icq ?io r f v o c d icq + io ? i ? i v o iq1 ad8011 a2 c p 2 z1 z1 = r1 || c1 z1 c d r l a1 a1 inp a3 figure 6. simplified block diagram
rev. c ?0 ad8011 (error current times the open-loop inverting input resistance) that re sults (see figure 7), a more exact low frequency closed-loop transfer function can be described as a g gr t r t g g a r t v i o f oo f o = + + = ++ 11 for noninverting ( g is positive). a v o f o g g a r t = ++ 1 1 C for inverting ( g is negative). where g is the ideal gain as previously described. with r i = t o /a o (open-loop inverting input resistance), the second expression (positive g ) clearly relates to the classical voltage feedback op amp equation with t o omitted due to its relatively m uch higher value and thus insignificant effect. a o a nd t o are the open-loop dc voltage and transresistance gains of the amplifier, respectively. these key transfer variables can be described as a rg mf a g mc r o = 12 1 1 | | ( C ) and t ra o = 12 2 | | therefore r g mc r g mf i = 1 1 2 C where g mc is the positive feedback transconductance (not shown) and 1/g mf is the thermal emitter resistance of devices d1/d2 and q3/q4. the g mc r1 product has a design value that results in a negative dc open-loop gain of typically C 2500 v/v (see figure 8). r s l n t o (s) a o (s) v p z i ie l i r n c p r f +v s ? s l s r l c l v o l s z i = open loop input impedance = c i || r l figure 7. z i = open-loop input impedance though atypical of conventional cf or vf amps, this negative open-loop voltage gain results in an input referred error term (v p C v o /g = g/a o + r f /t o ) that will typically be negative for g, greater than +3/C 4. as an example, for g = 10, a o = C 2500, and t o = 1.2 m ? , results in an error of C 3 mv using the a v derivation above. this analysis assumes perfect current sources and infinite transistor v a s. (q3, q4 output conductances are assumed zero.) these assumptions result in actual versus model open-loop voltage gain and associated input referred error terms being less accurate for low gain (g) noninverting operation at the frequencies below the open-loop pole of the ad8011. this is primarily a result of the input signal (v p ) modulating the output conductances of q3/q4, resulting in r i less negative than derived here. for inverting operation, the actual versus model dc error terms are relatively much less. 1e+03 1e+04 1e+05 1e+06 1e+07 1e+08 1e+09 80 70 60 50 40 20 10 frequency (hz) 30 gain (db ) ?0 phase (degrees) ?00 ?10 ?20 ?60 phase gain 0 ?0 ?0 ?0 ?70 ?80 ?90 ?00 ?30 ?40 ?50 a o (s) figure 8. open-loop voltage gain and phase ac transfer characteristics the ac small signal transfer derivations below are based on a simplified single-pole model. though inaccurate at frequencies approaching the closed-loop bw (clbw) of the ad8011 at low noninverting external gains, they still provide a fair approxima- tion and an intuitive understanding of its primary ac small signal characteristics. for inverting operation and high noninverting gains, these trans fer equations provide a good approximation to the actual ac performance of the device. to accurately quantify the v o versus v p relationship, a o (s) and t o (s) need to be derived. this can be seen by the following nonexpanded noninverting gain relationship vsvs g g as r ts op o f o ()/ () [] [] = ++ 1 with as rg mf a g mc r s g mc r o () || C C = 12 11 1 11 where r1 is the input resistance to a2/a2b, and 1 (equal to cd r1 a2) is the open-loop dominate time constant, and t s ar s o () || = + 21 2 11
rev. c ad8011 ?1 1e+03 1e+04 1e+05 1e+06 1e+07 1e+08 1e+09 frequency (hz) 140 120 100 80 60 20 0 40 gain (db ) 0 phase (degrees) ?0 ?0 ?20 ?60 ?00 ?40 ?80 phase gain t o (s) figure 9. open-loop transimpedance gain note that the ac open-loop plots in figures 8, 9, and 10 are based on the full spice ad8011 simulations and do not include external parasitics (see equations below). nevertheless, these ac loop equations still provide a good approximation to simulated and actual performance up to the clbw of the amplifier. typi- cally, g mc r1 is C 4, resulting in a o (s) having a right half plane pole. in the time domain (inverse laplace of a o ), it appears as unstable, causing v o to exponentially rail out of its linear region. when the loop is closed however, the bw is greatly extended and the transimpedance gain, t o (s), overrides and directly controls the amplifiers stability behavior due to z i approaching 1/2 g mf for s>>1/ 1 (see figure 10). this can be seen by the z i (s) and a v (s) noninverting transfer equations below. zs g mc r s g mc r g mf s i () ( C ) C () = + ? ? ? ? ? ? ? ? + 11 1 11 1 211 as g g a r t s g g mf t r t v o f oo f o () = ++ ? ? ? ? ? ? + ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? 11 2 1 1e+03 1e+04 1e+05 1e+06 1e+07 1e+08 1e+09 400 370 340 310 280 220 190 frequency (hz) 250 resistance () 20 phase (degrees) 0 ?0 ?0 ?20 160 130 100 ?40 ?60 ?80 ?0 ?0 ?00 series 1 impedance z i (s) series 2 phase figure 10. open-loop inverting input impedance z i (s) goes positive real and approaches 1/2 g mf as approaches (g mc r1 C 1)/ 1. this results in the input resistance for the a v (s) complex term being 1/2 g mf , the parallel thermal emitter resis tances of q3/q4. using the computed clbw from a v (s) and the nominal design values for the other parameters, results in a closed-loop 3 db bw equal to the open-loop corner frequency (1/2 1) 1 /[g/(2 g mf t o ) + r f /t o ]. for a fixed r f , the 3 db bw is controlled by the r f /t o term for low gains and g/(2 g mf t o ) for high gains. for example, using nominal design parameters and r 1 = 1 k ? (which results in a nominal t o of 1.2 m ? ), the computed bw is 80 mhz for g = 0 (inverting i-v mode w ith r n removed) and 40 mhz for g = +10/ C 9. driving capacitive loads the ad8011 was designed primarily to drive nonreactive loads. if driving loads with a capacitive component is desired, the best settling response is obtained by the addition of a small series resistance as shown in figure 11. the accompanying graph shows the optimum value for r series versus capacitive load. it is worth noting that the frequency response of the circuit when driving large capacitive loads will be dominated by the passive roll-off of r series and c l . 1k r l 1k c l r series 1k ad8011 figure 11. driving capacitive load
rev. c ?2 ad8011 40 30 20 01 0 1 5 2 0 2 5 c l (pf) 10 r series () 5 figure 12. recommended r series vs. capacitive load for 30 ns settling to 0.1% optimizing flatness as mentioned, the previous ac transfer equations are based on a simplified single-pole model. due to the device s internal para- sitics (primarily c p 1/c p 1b and c p 2 in figure 6) and external package/board parasites (partially represented in figure 12) the computed bw, using the previous v o (s) equation, typically will be lower than the ad8011 s measured small signal bw. see data sheet bode plots. with only internal parasitics included, the bw is extended due to the complex pole pairs created primarily by c p 1/c p 2b and c p 2 versus the single-pole assumption shown above. this results in a design controlled , closed-loop damping factor ( ) of nominally 0.6 resulting in the clbw increasing by approxi- mately 1.3 higher than the computed single-pole value above for optimized external gains of +2/? . as external noninverting gain (g) is increased, the actual closed-loop bandwidth versus the computed single-pole ac response is in closer agreement. inverting pin and external component capacitance (designated c p ) will further extend the clbw due to the closed-loop zero created by c p and r n r f when operating in the noninverting mode. using proper r f component and layout techniques (see the layout considerations section), this capacitance should be about 1.5 pf. this results in a further incremental bw increase of almost 2 (versus the computed value) for g = +1 decreasing and approach- ing its complex pole pair bw for gains approaching +6 or higher. as previously discussed, the single-pole response begins to corre- late well. note that a pole is also created by 1/2 g mf and c p , which prevents the ad8011 from becoming unstable. this parasitic has the greatest effect on bw and peaking for low positive gains as the data sheet bode plots clearly show. for inverting operation, c p has relatively much less effect on clbw variation. 11 10 9 8 7 5 4 3 6 2 1 1 10 100 500 frequency ( mhz ) gain (db) r f = 1k r f = 750 v s = 5v g = +2 v in = 200mv figure 13. flatness vs. feedback output pin and external component capacitance (designated c l ) will further extend the devices bw and can also cause peaking below and above the clbw if too high. in the time domain, poor step settling characteristics (ringing up to about 2 ghz and excessive overshoot) can result. for high c l values greater than about 5 pf, an external series damping resistor is recom- mended. for light loads, any output capacitance will reflect on a2 s output (z2 of buffer a3) as both added capacitance near the clbw (clbw > f t /b) and eventually negative resistance at much higher frequencies. these added effects are proportional to the load c. this reflected capacitance and negative resistance has the effect of both reducing a2 s phase margin and causing high frequency, l c, peaking respectively. using an external series resistor (as previously specified) reduces these unwanted effects by creating a reflected zero to a2 s output, which will reduce the peaking and eliminate ringing. for heavy resistive loads, relatively more load c would be required to cause these same effects. high inductive parasitics, especially on the supplies and inverting/ noninverting inputs, can cause modulated low level r f ringing on the output in the transient domain. proper r f component and board layout practices need to be observed. relatively high para- sitic lead inductance (roughly l >15 nh) can result in l c underdamped ringing. here l/c means all associated input pins, external components, and lead frame strays, including collector to substrate device capacitance. in the ac domain, this l c resonance effect would typically not appear in the pass band of t he amplifier but would appear in the open-loop response at frequencies well above the clbw of the amplifier.
rev. c ad8011 ?3 increasing bw at high gains as presented previously, for a fixed r f (feedback gain setting resistor), the ad8011 clbw will decrease as r n is reduced (increased g ). this effect can be minimized by simply reducing r f and partially restoring the devices optimized bw for gains greater than +2/C 1. note that the ad8011 is ac optimized (high bw and low peaking) for a v = +2/C 1 and r f = 1 k ? . using this optimized g as a reference and the previous v o (s) equations, the following relationships result: r f = 1k ? + 2 C g /2 gm for g = 1+ r f /r n (noninverting) or r f = 1 k ? + g + 1/2 gm for g = C r f / r n (inverting). using 1/2 gm equal to 120 ? results in a r f of 500 ? for g = +5/C 4 and a corresponding r n of 125 ? . this will extend the ad8011 s bw to near its optimum design value of typically 180 mhz at r l = 1 k ? . in general, for gains greater than +7/ C 6, r f should not be reduced to values much below 400 ? or else ac peaking can result. using this r f value as the lower limit will result in bw restoration near its optimized value to the upper g values specified. gains greater than about +7/ C 6 will result in clbw reduction. the derivations above are just approximations. driving a single-supply a/d converter new cmos a/d converters are placing greater demands on the amplifiers that drive them. higher re solutions, faster conversion rates, and input switching irregularities require superior settling characteristics. in addition, these devices run off a single 5 v supply and consume little power, so good single-supply operation with low power consumption are very important. the ad8011 is well positioned for driving this new class of a/d converters. figure 14 shows a circuit that uses an ad8011 to drive an ad876, a single-supply, 10-bit, 20 msps a/d converter that requires only 140 mw. using the ad8011 for level shifting and driving, the a/d exhibits no degradation in performance compared to when it is driven from a signal generator. 3.6v 1.6v ad8011 +5v 10f r2 1k r3 1.65k r1 499k 3.6v v in 50 0.1f 1.6v 1v 0v 100 ad876 +1.6v +3.6v reft refb 0.1f 0.1f figure 14. ad8011 driving the ad876 the analog input of the ad876 spans 2 v centered at about 2.6 v. the resistor network and bias voltages provide the level shifting and gain required to convert the 0 v to 1 v input signal to a 3.6 v to 1.6 v range that the ad876 wants to see. biasing the noninverting input of the ad8011 at 1.6 v dc forces the inverting input to be at 1.6 v dc for linear operation of the amplifier. when the input is at 0 v, there is 3.2 ma flowing out of the summing junction via r1 (1.6 v/499 ? ). r3 has a current of 1.2 ma flowing into the summing junction (3.6 v C 1.6 v)/1.65 k ? . the difference of these two currents (2 ma) must flow through r2. this current flows toward the summing junction and requires that the output be 2 v higher than the summing junction or at 3.6 v. when the input is at 1 v, there is 1.2 ma flowing into the sum- ming junction through r3 and 1.2 ma flowing out through r1. these currents balance and leave no current to flow through r2. thus, the output is at the same potential as the inverting input or 1.6 v. the input of the ad876 has a series mosfet switch that turns on and off at the sampling rate. this mosfet is connected to a hold capacitor, internal to the device. the on impedance of the mosfet is about 50 ? , while the hold capacitor is about 5 pf. in a worst-case condition, the input voltage to the ad876 will change by a full-scale value (2 v) in one sampling cycle. when the input mosfet turns on, the output of the op amp will be connected to the charged hold capacitor through the series resis- tance of the mosfet. without any other series resistance, the instantaneous current that flows would be 40 ma. this would cause settling problems for the op amp. the series 100 ? resistor limits the current that flows instantane- ously to about 13 ma after the mosfet turns on. this resistor cannot be made too large or the high frequency performance will be affected. the sampling mosfet of the ad876 is closed for only half of each cycle or for 25 ns. approximately seven time constants are required for settling to 10 bits. the series 100 ? resistor, the 50 ? on resistance, and the hold capacitor create a 750 ps time constant. these values leave a comfortable margin for settling. obtaining the same results with the op amp a/d combination as compared to driving with a signal generator indicates that the op amp is settling fast enough. overall, the ad8011 provides adequate buffering for the ad876 a/d converter without introducing distortion greater than that of the a/d converter by itself.
rev. c ?4 ad8011 layout considerations the specified high speed performance of the ad8011 requires careful attention to board layout and component selection. t able i shows the recommended component values for the ad8011. proper r f design techniques and low parasitic component selec- tion are mandatory. table i. typical bandwidth vs. gain setting resistors small signal ? db bw (mhz), gain r f ( )r g ( )r t ( )v s = 5 v C 1 1000 1000 52.3 150 C 2 1000 499 54.9 130 C 10 499 49.9 140 +1 1000 49.9 400 +2 1000 1000 49.9 250 +10 422 47.5 49.9 100 +6 1000 200 49.9 70 +6 500 100 49.9 170 r t chosen for 50 ? characteristic input impedance. r o chosen for characteristic output impedance. the pcb should have a ground plane covering all unused por tions of the component side of the board to provide a low impedance ground path. the ground plane should be removed from the area near the input pins to reduce stray capacitance. chip capacitors should be used for supply bypassing (see fig ure 15). one end should be connected to the ground plane and the other within 1/8 in. of each power pin. an additional tan- talum electrolytic capacitor (4.7 f C 10 f) should be connected in parallel. the feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a minimum. capacitance greater than 1.5 pf at the inverting input will significantly affect high speed performance when operating at low noninverting gains. stripline design techniques should be used for long signal traces (greater than about 1 in.). these should be designed with the proper system characteristic impedance and be properly termi nated at each end. c1 0.01f c2 0.01f c4 10f c3 10f r t inverting configuration v in v out +v s ? s r g r f r o c1 0.01f c2 0.01f c4 10f c3 10f r t noninverting configuration v in +v s ? s v out r g r f r o figure 15. inverting and noninverting configurations
rev. c ad8011 ?5 outline dimensions 8-lead plastic dual in-line package [pdip] (n-8) dimensions shown in inches and (millimeters) seating plane 0.180 (4.57) max 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.060 (1.52) 0.050 (1.27) 0.045 (1.14) 8 1 4 5 0.295 (7.49) 0.285 (7.24) 0.275 (6.98) 0.100 (2.54) bsc 0.375 (9.53) 0.365 (9.27) 0.355 (9.02) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design compliant to jedec standards mo-095aa 0.015 (0.38) min 8-lead standard small outline package [soic] (r-8) dimensions shown in millimeters and (inches) 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 85 4 1 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-012aa
rev. c c01048??/03(c) ?6 ad8011 revision history location page 7/03?ata sheet changed from rev. b to rev. c. deleted all references to evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal format updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal renumbered figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal changes to figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 updated ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 changes to tpc 9 and 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 changes to tpc 13 and 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 changes to tpc 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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